FIG. 1 schematically illustrates a memory cell array of a conventional ROM, and FIG. 2 is a timing diagram for read operation of the mask ROM of FIG. 1. In FIG. 1, reference symbols MC1-MC5 represent memory cells, BL(i-1) to BL(i+1) bit lines, WL(0) through WL(m) word lines, and YA(0) through YA(15) and YB(0) through YB(3) column select lines (or column select signals). Column select transistors controlled by the column select signals YA(0) to YB(3) select one of the bit lines. The selected bit line is electrically coupled to a sense amplifier circuit and thereby a data bit on the selected bit line can be sensed and amplified.
A read operation of a ROM is typically divided into three periods: bit line precharge, data sensing, and data output periods. At the beginning of the data read operation (i.e., the precharge period), all the bit lines is precharged to a predetermined voltage (e.g., 1 V to 2 V) in order to enhance the sensing gain and increase the data sensing speed. Thereafter, the voltage level on the selected bit line coupled with a selected memory cell is sensed and it is determined whether the selected cell is an "on-cell" that presents a current path between a corresponding bit line and a voltage supply of a reference voltage (e.g., ground voltage), or "off-cell" doing no current path between them. It is commonly assumed that the on-cell is programmed to a logic "0" and the off-cell a logic "1". Lastly, the sensed data is output to exterior.
During such a read operation of the prior art ROM, however, there is a possibility that reading errors will occur, depending on the selection of particular cells, the cell selection sequence and the programmed states of the selected cells. An example of the reading error mechanism will be explained with reference to FIGS. 1 and 2 below.
Referring again to FIG. 1, the memory cells MC1-MC3 are assumed on-cells and the other cells MC4 and MC5 off-cells. As shown in FIG. 2, it is also assumed that cells MC1-MC3 are selected in the read cycles I, II and III in order, respectively. No error occurs in cycles I and II associated with reading cells MC1 and MC2. During the cycles I and II in which word line WL(i) and column select lines YA(0), YA(2) and YB(1) are selected, the bit lines BL(i-1) and BL(i+1) are maintained at their precharge levels since the cells MC1 and MC2 are off-cells. In order to read a data from the cell MC3 in cycle III, when word line WL(j) and column select lines YA(1) and YB(1) are activated and bit line BL(i) is precharged, the bit lines BL(i-1) and BL(i+1) begin to discharge since cells MC4 and MC5 are on-cells, causing the capacitive coupling between bit lines BL(i-1), BL(i) and BL(i+1). This bit line coupling effect is more serious if at least one of the cells MC4 and MC5 has a current driving capability larger than that of a normal on-cell, i.e., if either or both of the cells MC4 are "best on-cells". The bit line coupling prevents the bit line BL(i) from being precharged sufficiently. Therefore, when the off-cell MC3 coupled to the bit line BL(i) under-precharged is sensed, the voltage on the bit line BL(i) cannot be amplified up to an appropriate level by a sense amplifier during a given sensing time, leading to a delay in the data sensing or a reading error that the cell MC3 is identified as an on-cell.
As is clear from the above discussion, there exists a need for a mask ROM device and method for solving the bit line coupling problem to improve read speed and prevent read fail.